1. Field of the Invention
The present invention relates, in general, to a method of manufacturing a build-up printed circuit board (build-up PCB), and more particularly, to a method of manufacturing a build-up PCB, in which the core circuit layer of a build-up PCB is formed through a dry metal seed layer forming process including ion beam surface treatment and vacuum deposition, thereby realizing a highly reliable fine circuit in an environmentally friendly manner.
2. Description of the Related Art
Presently, build-up PCBs have been manufactured using a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).
In particular, a subtractive process is applied to HDI (high density interconnection) products, and a subtractive process and MSAP are applied to UT-CSP (ultra thin-chip scale package) and BGA (ball grid array) products. Further, in the case of FCBGA (flip chip BGA), a core layer and a build-up outer layer including 2F2B/3F3B are formed using a subtractive process and SAP, respectively, and furthermore, a seed layer is formed through electroless plating, thereby realizing a fine circuit.
In this regard, according to a first conventional technique, FIGS. 1A and 1B are flowcharts respectively illustrating the processes of forming the core layer and the outer layer of a build-up PCB.
With reference to FIG. 1A and FIGS. 2A to 2G, the method of forming the core layer of the build-up PCB using a subtractive process according to the first conventional technique is described below.
First, a resin substrate 11 having metal layers 12 laminated on both surfaces thereof is subjected to typical etching and drilling to thus form a through hole 13 (FIGS. 2A and 2B). Subsequently, the surface of the substrate having the through hole 13 is subjected to desmearing and then electroless plating to thus form an electroless metal layer 14 (FIG. 2C). Through electroplating, a metal panel plating layer 15 is formed (FIG. 2D). The through hole 13 is filled with a conductive paste 16 (FIG. 2E), after which a dry film 17 is applied on a predetermined region corresponding to a circuit pattern, including the through hole 13 (FIG. 2F). The unnecessary portions of the metal layers are removed through typical exposure/development and etching, and then the dry film 17 is removed, thus completing the procedure for forming the core circuit layer (FIG. 2G). Before the following outer layer forming process is performed, the substrate is subjected to typical surface treatment, such as CZ treatment, as known in the art, and then an insulating layer is laminated thereon (not shown).
In addition, with reference to FIG. 1B and FIGS. 3A to 3F, the process of forming the outer layer of the build-up PCB using MSAP according to the first conventional technique is described below. For convenience, the description of the build-up process on the core layer is omitted, and only the outer layer forming process is described.
First, a resin substrate 21 having metal layers 22 laminated on both surfaces thereof is half-etched and then subjected to typical etching and drilling to thus form a blind via hole 23 (FIGS. 3A and 3B). Thereafter, the surface of the substrate having the blind via hole 23 is subjected to desmearing and then electroless plating to thus form an electroless metal layer 24 (FIG. 3C). Thereafter, a dry film 26 is applied on a predetermined region, other than the region corresponding to a circuit pattern, including the via hole 23 (FIG. 3D). Using the dry film as a resist, a metal pattern plating layer 27 is formed through electroplating (FIG. 3E). Thereafter, the dry film 26 is removed, and the unnecessary portions of the metal layers are removed through flash etching, thus completing the patterning process (FIG. 3F).
According to a second conventional technique, the processes of forming the core layer and the outer layer of a build-up PCB are illustrated in flowcharts of FIGS. 4A and 4B, respectively.
With reference to FIG. 4A and FIGS. 5A to 5G, the process of forming the core layer of the build-up PCB using a subtractive process according to the second conventional technique is described below.
First, a resin substrate 31 including metal layers 32 having a thickness of about 12 μm laminated on both surfaces thereof is subjected to typical etching and drilling, thus forming a through hole 13 having a diameter of about 350 μm (FIGS. 5A and 5B). Subsequently, the surface of the substrate having the through hole 33 is subjected to desmearing and then electroless plating, thus forming an electroless metal layer 34 about 1˜3 μm thick (FIG. 5C). Through electroplating, a metal panel plating layer 35 about 18 μm thick is formed (FIG. 5D). The through hole 33 having the electrolytic metal layer 35 is filled with a conductive paste 36 (FIG. 5E), after which a dry film 37 is applied on a predetermined region corresponding to a circuit pattern, including the through hole 33 (FIG. 5F). The unnecessary portions of the metal layers are removed via typical exposure/development and etching, and then the dry film 37 is removed, thereby completing the procedure for forming the core circuit layer (FIG. 5G). Before the following outer layer forming process progresses, the substrate is subjected to typical surface treatment, such as CZ treatment, as known in the art, and then an insulating layer is laminated thereon (not shown).
In addition, with reference to FIG. 4B and FIGS. 6A to 6F, the process of forming the outer layer of the build-up PCB using SAP according to the second conventional technique is described below. For convenience, the description of the build-up process on the core layer is omitted, and only the outer layer forming process is described.
First, a resin substrate 41 having metal layers 42 laminated on both surfaces thereof, for example, an ABF (Ajinomoto Build-up Film) about 35 μm thick, is subjected to typical etching and drilling to form a blind via hole 43 having a diameter of about 75 μm (FIGS. 6A and 6B). Then, the surface of the substrate having the blind via hole 43 is subjected to desmearing and then electroless plating, therefore forming an electroless metal layer 44 about 1±0.3 μm thick (FIG. 6C). Then, a dry film 45 is applied on a predetermined region, other than the region corresponding to a circuit pattern including the blind via hole 43 (FIG. 6D). Using the dry film as a resist, a metal pattern plating layer 46 is formed through electroplating (FIG. 6E). Then, the dry film 45 is removed, and the unnecessary portions of the metal layers are removed through flash etching, thus completing the patterning process (FIG. 6F).
As such, examples of the material for resin substrate depending on the type of product include epoxy resins, such as FR-4, BT (Bismaleimide Triazine), ABF, etc.
For instance, in the case of BGA and UT-CSP produced through a subtractive process and MSAP, which comprises a BT insulating material, the surface profile of the material is at least 1 μm, and in the subtractive process, a fine circuit having a pitch not larger than 80 μm (line/space=40/40 μm) is difficult to realize. In the MSAP, since the thickness of the metal layer varies due to half-etching, a fine circuit having a pitch on the order of about 50 μm (line/space=25/25 μm) may be obtained.
In the group of FCBGA products, the core layer is typically formed using an FR-4 resin substrate through a subtractive process to thus realize a circuit having a pitch of about 100 μm (line/space=50/50 μm), and the build-up outer layer is prepared using an ABF resin substrate through SAP to attain a fine circuit having a pitch of about 36 μm (line/space=18/18 μm). As such, however, the fine circuit of the core layer is difficult to realize, attributable to the surface roughness of the resin substrate material and the limitation of the subtractive process itself.
Further, in the group of FCBGA products, in which a multilayered substrate is manufactured using an ABF insulating material through SAP, as illustrated in FIG. 7, a subtractive process is applied to a core layer (which is composed of 1st˜2nd layers 52a, 52b), and SAP is applied to an outer layer (which is composed of 3rd˜6th layers 55a, 55b, 57a, 57b). In particular, in order to form the circuit, the outer layer forming process, comprising electroless plating for forming a seed layer about 1˜3 μm thick, plating, stripping, and flash etching, is repeated two times. Thereby, via holes 53 and circuit patterns 52a, 52b, 55a, 55b, 57a, 57b are formed in resin substrates 51, 54a, 54b, 56a, 56b. Subsequently, an solder resist 58a, 58b is applied and a solder resist open part 59a, 59b is formed. Thereby, a FCBGA having a total of six layers is completed.
However, the use of expensive ABF material results in increased process cost and thus a high product price. In the case in which the SAP is applied, the surface profile of the ABF material is at least 1 μm, leading to a large surface roughness and a pitch of 36 μm (line/space=18/18 μm). Further, there are limitations in realizing a fine circuit through wet surface treatment and electroless chemical plating.
With the demand for light, slim, short and small PCBs, many manufacturers have attempted to develop insulating material for realizing a fine circuit and exhibiting high functionality in order to increase signal transfer rates on circuits. According to the above development trend, the number of signals that are input and output is increased, and thus highly reliable fine circuit is required. However, conventional SAP suffers because a metal seed layer is formed through a wet process including wet surface treatment and electroless plating, undesirably increasing the surface roughness, thus making it impossible to realize a fine circuit. As well, a large amount of waste is generated, causing environmental problems.